{"id":900493,"date":"2023-02-10T14:50:16","date_gmt":"2023-02-10T06:50:16","guid":{"rendered":"https:\/\/www.bihec.com\/stanford-research-systems\/?p=900493"},"modified":"2023-02-10T14:50:16","modified_gmt":"2023-02-10T06:50:16","slug":"srs-cg635-clock-generator%e6%97%b6%e9%92%9f%e5%8f%91%e7%94%9f%e5%99%a8","status":"publish","type":"post","link":"https:\/\/www.bihec.com\/stanford-research-systems\/srs-cg635-clock-generator%e6%97%b6%e9%92%9f%e5%8f%91%e7%94%9f%e5%99%a8\/","title":{"rendered":"SRS CG635 Clock Generator,Stanford research systems CG635\u65f6\u949f\u53d1\u751f\u5668"},"content":{"rendered":"

SRS CG635 Clock Generator<\/a>,Stanford research systems CG635<\/a>\u65f6\u949f\u53d1\u751f\u5668<\/p>\n

CG635\u4ea7\u751f\u6781\u4e3a\u7a33\u5b9a\u9891\u7387\u8303\u56f4\u4ece1\u03bcHz\u52302.05GHz\u7684\u65b9\u6ce2\u65f6\u949f\u3002\u8be5\u4eea\u5668\u5177\u6709\u9ad8\u9891\u7387\u5206\u8fa8\u7387\uff0c\u4f4e\u6296\u52a8\uff0c\u5feb\u901f\u8f6c\u6362\u65f6\u95f4\u548c\u7075\u6d3b\u7684\u8f93\u51fa\u7535\u5e73\u7b49\u7279\u70b9\u4f7f\u4e4b\u6210\u4e3a\u4efb\u4f55\u6570\u5b57\u5143\u4ef6\u3001\u7cfb\u7edf\u6216\u7f51\u7edc\u6d4b\u8bd5\u7684\u6700\u7406\u60f3\u9009\u62e9\u3002<\/p>\n

\u00b7\u65f6\u949f\u9891\u73871\u03bcHz\u52302.05GHz<\/p>\n

\u00b7\u968f\u673a\u6296\u52a8<1 ps rms<\/p>\n

\u00b716\u4f4d\u9891\u7387\u5206\u8fa8\u7387<\/p>\n

\u00b780 ps\u7684\u4e0a\u5347\u548c\u4e0b\u964d\u65f6\u95f4<\/p>\n

\u00b7CMOS\uff0cPECL\uff0cECL\uff0cLVDS\uff0cRS – 485\u7684\u8f93\u51fa<\/p>\n

\u00b7\u76f8\u4f4d\u63a7\u5236\u548c\u65f6\u95f4\u8c03\u5236<\/p>\n

\u00b7 OCXO and rubidium\u65f6\u57fa\uff08\u9009\u914d\uff09<\/p>\n

\n
\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

CG635 Stanford research<\/a> systems Clock Generator Specifications<\/p>\n<\/td>\n<\/tr>\n

\n

Frequency<\/p>\n<\/td>\n<\/tr>\n

Range<\/span><\/td>\nDC, 1 \u00b5Hz to 2.05 GHz<\/span><\/td>\n<\/tr>\n
Resolution<\/span><\/td>\n16 digits (f \u2265 10 kHz), 1 pHz (f < 10 kHz)<\/span><\/td>\n<\/tr>\n
Accuracy<\/span><\/td>\n\u0394f < \u00b1(2 \u00d7 10-19<\/span><\/sup>\u00a0+ timebase error)\u00a0\u00d7 f<\/span><\/td>\n<\/tr>\n
Settling time<\/span><\/td>\n<30 ms<\/span><\/td>\n<\/tr>\n
\n

Timebase\u00a0(20 \u00b0C to 30 \u00b0C ambient)<\/span><\/p>\n<\/td>\n<\/tr>\n

Stability<\/span><\/td>\n<5 ppm (std. timebase)
\n<0.01 ppm (opt. 02 OCXO)
\n<0.0001 ppm (opt. 03 Rb timebase)<\/span><\/td>\n<\/tr>\n
Aging<\/span><\/td>\n<5 ppm\/year (std. timebase)
\n<0.2 ppm\/year (opt. 02 OCXO)
\n<0.0005 ppm\/year (opt. 03 Rb timebase)<\/span><\/td>\n<\/tr>\n
External input<\/span><\/td>\n10 MHz \u00b1 10 ppm, sine >0.5 Vpp, 1 k\u03a9<\/span><\/td>\n<\/tr>\n
Output<\/span><\/td>\n10 MHz, 1.41 Vpp sine into 50 \u03a9<\/span><\/td>\n<\/tr>\n
\n

Phase Noise\u00a0(at 622.08 MHz)<\/span><\/p>\n<\/td>\n<\/tr>\n

100 Hz offset<\/span><\/td>\n<-90 dBc\/Hz<\/span><\/td>\n<\/tr>\n
1 kHz offset<\/span><\/td>\n<-100 dBc\/Hz<\/span><\/td>\n<\/tr>\n
10 kHz offset<\/span><\/td>\n<-100 dBc\/Hz<\/span><\/td>\n<\/tr>\n
100 kHz offset<\/span><\/td>\n<-110 dBc\/Hz<\/span><\/td>\n<\/tr>\n
\n

Jitter and Wander<\/p>\n<\/td>\n<\/tr>\n

Jitter (rms)<\/span><\/td>\n<1 ps (1 kHz to 5 MHz bandwidth)<\/span><\/td>\n<\/tr>\n
Wander (p-p)<\/span><\/td>\n<20 ps (10 s persistence)<\/span><\/td>\n<\/tr>\n
\n

Time Modulation\u00a0(rear-panel input)<\/span><\/p>\n<\/td>\n<\/tr>\n

Input impedance<\/span><\/td>\n1 k\u03a9<\/span><\/td>\n<\/tr>\n
Sensitivity<\/span><\/td>\n1 ns\/V, \u00b15 %<\/span><\/td>\n<\/tr>\n
Range<\/span><\/td>\n\u00b15 ns<\/span><\/td>\n<\/tr>\n
Bandwidth<\/span><\/td>\nDC to greater than 10 kHz<\/span><\/td>\n<\/tr>\n
\n

Phase Setting<\/p>\n<\/td>\n<\/tr>\n

Range<\/span><\/td>\n\u00b1720\u00b0 (max. step size \u00b1360\u00b0)<\/span><\/td>\n<\/tr>\n
Resolution<\/span><\/td>\n<14 ps<\/span><\/td>\n<\/tr>\n
Slew time<\/span><\/td>\n<300 ms<\/span><\/td>\n<\/tr>\n
\n

Q and \u2212Q Outputs<\/p>\n<\/td>\n<\/tr>\n

Outputs<\/span><\/td>\nFront-panel BNC connectors<\/span><\/td>\n<\/tr>\n
Frequency range<\/span><\/td>\nDC to 2.05 GHz<\/span><\/td>\n<\/tr>\n
High level<\/span><\/td>\n-2.00 V \u2264 VHIGH<\/span><\/sub>\u00a0\u2264 +5.00 V<\/span><\/td>\n<\/tr>\n
Amplitude<\/span><\/td>\n200 mV \u2264 VAMPL<\/span><\/sub>\u00a0\u2264 1.00 V
\n(VAMPL\u00a0<\/span><\/sub>\u2261 VHIGH<\/span><\/sub>\u00a0– VLOW<\/span><\/sub>)<\/span><\/td>\n<\/tr>\n
Level resolution<\/span><\/td>\n10 mV<\/span><\/td>\n<\/tr>\n
Level error<\/span><\/td>\n<1 % + 10 mV<\/span><\/td>\n<\/tr>\n
Transition time<\/span><\/td>\n<100 ps (20 % to 80 %)<\/span><\/td>\n<\/tr>\n
Symmetry<\/span><\/td>\n<100 ps departure from nominal 50 %<\/span><\/td>\n<\/tr>\n
Source impedance<\/span><\/td>\n50 \u03a9(\u00b11 %)<\/span><\/td>\n<\/tr>\n
Load impedance<\/span><\/td>\n50 \u03a9 to ground on both outputs<\/span><\/td>\n<\/tr>\n
Preset levels<\/span><\/td>\nPECL, LVDS, +7 dBm, ECL<\/span><\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<\/div>\n
\n
<\/div>\n<\/div>\n
\n
\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n\n
\n

CMOS Output<\/p>\n<\/td>\n<\/tr>\n

Output<\/span><\/td>\nFront-panel BNC<\/span><\/td>\n<\/tr>\n
Frequency range<\/span><\/td>\nDC to 250 MHz<\/span><\/td>\n<\/tr>\n
Low level<\/span><\/td>\n-1.00 V \u2264 VLOW<\/span><\/sub>\u2264 +1.00 V<\/span><\/td>\n<\/tr>\n
Amplitude<\/span><\/td>\n500 mV \u2264 VAMPL<\/span><\/sub>\u00a0\u2264 6.00 V
\n(VAMPL<\/span><\/sub>\u00a0\u2261 VHIGH<\/span><\/sub>\u00a0– VLOW<\/span><\/sub>)<\/span><\/td>\n<\/tr>\n
Level resolution<\/span><\/td>\n10 mV<\/span><\/td>\n<\/tr>\n
Level error<\/span><\/td>\n<2 % of VAMPL<\/span><\/sub>+ 20 mV<\/span><\/td>\n<\/tr>\n
Transition time<\/span><\/td>\n<1 ns (20 % to 80 %)<\/span><\/td>\n<\/tr>\n
Symmetry<\/span><\/td>\n<500 ps departure from nominal 50 %<\/span><\/td>\n<\/tr>\n
Source impedance<\/span><\/td>\n50 \u03a9 (reverse terminates cable reflection)<\/span><\/td>\n<\/tr>\n
Load impedance<\/span><\/td>\nUnterminated 50 \u03a9 cable of any length<\/span><\/td>\n<\/tr>\n
Attenuation (50 \u03a9 load)<\/span><\/td>\nOutput levels are divided by 2<\/span><\/td>\n<\/tr>\n
Preset levels<\/span><\/td>\n1.2 V, 1.8 V, 2.5 V, 3.3 V or 5.0 V<\/span><\/td>\n<\/tr>\n
\n

RS-485 Output<\/p>\n<\/td>\n<\/tr>\n

Output<\/span><\/td>\nRear-panel RJ-45<\/span><\/td>\n<\/tr>\n
Frequency range<\/span><\/td>\nDC to 105 MHz<\/span><\/td>\n<\/tr>\n
Transition time<\/span><\/td>\n<800 ps (20 % to 80 %)<\/span><\/td>\n<\/tr>\n
Clock output<\/span><\/td>\nPin 7 and pin 8 drive twisted pair<\/span><\/td>\n<\/tr>\n
Source impedance<\/span><\/td>\n100 \u03a9 between pin 7 and pin 8<\/span><\/td>\n<\/tr>\n
Load impedance<\/span><\/td>\n100 \u03a9 between pin 7 and pin 8<\/span><\/td>\n<\/tr>\n
Logic levels<\/span><\/td>\nVLOW<\/span><\/sub>\u00a0= +0.8 V, VHIGH<\/span><\/sub>\u00a0= +2.5 V<\/span><\/td>\n<\/tr>\n
Recommended cable<\/span><\/td>\nStraight-through Category-6<\/span><\/td>\n<\/tr>\n
\n

LVDS Output\u00a0(EIA\/TIA-644)<\/span><\/p>\n<\/td>\n<\/tr>\n

Output<\/span><\/td>\nRear-panel RJ-45<\/span><\/td>\n<\/tr>\n
Frequency range<\/span><\/td>\nDC to 2.05 GHz<\/span><\/td>\n<\/tr>\n
Transition time<\/span><\/td>\n<100 ps (20 % to 80 %)<\/span><\/td>\n<\/tr>\n
Clock output<\/span><\/td>\nPin 1 and pin 2 to drive twisted pair<\/span><\/td>\n<\/tr>\n
Source impedance<\/span><\/td>\n100 \u03a9 between pin 1 and pin 2<\/span><\/td>\n<\/tr>\n
Load impedance<\/span><\/td>\n100 \u03a9 between pin 1 and pin 2<\/span><\/td>\n<\/tr>\n
Logic levels<\/span><\/td>\nVLOW<\/span><\/sub>\u00a0= +0.96 V, VHIGH<\/span><\/sub>\u00a0= +1.34 V<\/span><\/td>\n<\/tr>\n
Recommended cable<\/span><\/td>\nStraight-through Category-6<\/span><\/td>\n<\/tr>\n
\n

PRBS\u00a0(Opt. 01, EIA\/TIA-644)<\/span><\/p>\n<\/td>\n<\/tr>\n

Outputs<\/span><\/td>\nPRBS, -PRBS, CLK and -CLK<\/span><\/td>\n<\/tr>\n
Frequency range<\/span><\/td>\nDC to 1.55 GHz<\/span><\/td>\n<\/tr>\n
Level<\/span><\/td>\nLVDS on rear-panel SMA jacks<\/span><\/td>\n<\/tr>\n
PRBS generator<\/span><\/td>\nx7<\/span><\/sup>\u00a0+ x6<\/span><\/sup>\u00a0+ 1 for a length of 27<\/span><\/sup>\u00a0– 1 bits<\/span><\/td>\n<\/tr>\n
Transition time<\/span><\/td>\n<100 ps (20 % to 80 %)<\/span><\/td>\n<\/tr>\n
Load impedance<\/span><\/td>\n50 \u03a9 to ground on all outputs<\/span><\/td>\n<\/tr>\n
\n

General<\/p>\n<\/td>\n<\/tr>\n

Computer interfaces<\/span><\/td>\nGPIB and RS-232 std. All functions can be controlled through either\u00a0interface.<\/span><\/td>\n<\/tr>\n
Non-volatile memory<\/span><\/td>\nTen sets of instrument configurations can be stored and\u00a0recalled.<\/span><\/td>\n<\/tr>\n
Power<\/span><\/td>\n90 to 264 VAC, 47 to 63\u00a0Hz, 50\u00a0W<\/span><\/td>\n<\/tr>\n
Dimensions, weight<\/span><\/td>\n8.5″\u00d7 3.5″ \u00d7 13″ (WHL), 9\u00a0lbs.<\/span><\/td>\n<\/tr>\n
Warranty<\/span><\/td>\nOne year parts and labor on defects in materials and\u00a0workmanship<\/span><\/td>\n<\/tr>\n
<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n<\/div>\n<\/div>\n<\/div>\n
<\/div>\n
CG635\u65f6\u949f\u53d1\u751f\u5668<\/a>\nSRS CG635 Clock Generator<\/a>\nStanford research systems CG635<\/a><\/div>","protected":false},"excerpt":{"rendered":"

SRS CG635 Clock Generator,Stanford research systems CG635\u65f6\u949f\u53d1\u751f\u5668 CG635\u4ea7\u751f\u6781\u4e3a\u7a33\u5b9a\u9891\u7387\u8303\u56f4\u4ece1\u03bcHz\u52302.05GH <\/p>\n","protected":false},"author":29,"featured_media":900494,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"_vp_format_video_url":"","_vp_image_focal_point":[]},"categories":[3],"tags":[83,82,84],"yoast_head":"\nSRS CG635 Clock Generator\u65f6\u949f\u53d1\u751f\u5668<\/title>\n<meta name=\"description\" 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